ASICs Design Engineer ( Mixed Signal- mid career)

Job Details

New ideas are all around us, but only a few will change the world. That’s our focus at JPL. We ask the biggest questions, then search the universe for answers—literally. We build upon ideas that have guided generations, then share our discoveries to inspire generations to come. Your mission—your opportunity—is to seek out the answers that bring us one step closer. If you’re driven to discover, create, and inspire something that lasts a lifetime and beyond, you’re ready for JPL.

 

Located in Pasadena, California, JPL has a campus-like environment situated on 177 acres in the foothills of the San Gabriel Mountains and offers a work environment unlike any other: we inspire passion, foster innovation, build collaboration, and reward excellence.

Responsibilities

As a member of the Electronics Technology Group, you will be part of a core team developing ASICs for JPL’s next generation Instruments. Your efforts will pave the way for improving the scientific return of future NASA missions by realizing the performance, power, and mass benefits that ASICs provide. 

As a ASICS Design Engineer level 3, you will leverage your skills as an established mixed-signal designer in taking designs from requirements to validated Silicon.   Your contributions will be invaluable at all phases of the project from proposal to delivery and, as a member of the Instruments Division, you will be on the front line where engineering meets science.

 

Tasks include:

  • Design of mixed-signal circuit blocks including high resolution and high-speed A/D (SAR, Pipeline, Delta/Sigma, Time-Interleaved), D/A converters, and phase locked loops.
  • Digital signal processor design with RTL authoring through to physical implementation.
  • Full chip floor-planning, integration, and verification.
  • Conduct architectural trades at the chip and system level.
  • Generate requirements for the instantiation of your designs within high-order systems.
  • Mentoring of junior engineers in ASIC design and tool flow.

Qualifications

  • Bachelors degree in Electrical Engineering with a minimum of 6 years experience; Master’s degree in Electrical Engineering with a minimum of 4 years of experience or a PhD in Electrical Engineering with a minimum of 2 years of experience with directly applicable thesis work.
  • Previous design experience realizing mixed-signal circuits such as ADC, DACs, and PLLs.
  • Working knowledge of digitally-assisted analog techniques to correct for process variation and device mismatch.
  • Expert knowledge of the Cadence, Mentor, and Synopsys tool flow.
  • Understanding of industry standards and practices used in physical implementation and verification including sign-off (DRC/LEC/DFM/LVS/APC).
  • Demonstrated expertise in high-resolution and high-speed circuit design techniques for mixed mode circuits.
  • Strong knowledge of device physics.
  • Skilled in the use test equipment for design validation, including spectrum analyzers, mixed-signal oscilloscopes, and logic analyzers.
  • Excellent verbal and written communication skills.

Preferred Skills

  • Working knowledge of digital signal processing
  • Experience with RTL coding, simulation, debugging, synthesis, timing analysis, and design for test.
  • Knowledgeable in the effects of radiation on device performance.
  • Previous experience interfacing your designs with external analog transducers.

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