ASIC Physical Design Engineer, Level 3
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Located in Pasadena, California, JPL has a campus-like environment situated on 177 acres in the foothills of the San Gabriel Mountains and offers a work environment unlike any other: we inspire passion, foster innovation, build collaboration, and reward excellence.
We are looking to hire an experienced and dedicated ASIC Physical Design Engineer, Level 3, to join our team. As a member of the Electronics Technology Group, you will be part of a core team developing ASICs for JPL’s next generation Instruments. Your efforts will pave the way for improving the scientific return of future NASA missions by realizing the performance, power, and mass benefits that ASICs provide.
As an ASIC Physical Design Engineer, Level 3, you will leverage your skills as an established physical designer in taking designs from RTL to GDSII. Your contributions will be invaluable at all phases of the project from proposal to delivery and, as a member of the Instruments Division, you will be on the front line where engineering meets science.
- Full chip floor-planning, synthesis, P&R, formal verification, clock tree insertion, and timing closure.
- Ability to perform power analysis, load and decoupling analysis for mixed signal design.
- Ability to perform physical design verification methodology, and debugging LVS/DRC issues at all levels of hierarchy.
- Conduct architectural trades at the chip and system level.
- Generate requirements for the instantiation of designs within high-order systems.
- Mentoring of junior engineers in ASIC design and tool flow.
- Bachelors degree in Electrical Engineering with a minimum of 6 years of experience; Master’s with 4 years of experience, or a PhD with 2 years of experience & directly applicable thesis work.
- Expert knowledge of the Cadence, Mentor, and Synopsys tool flows.
- Understanding of industry standards and practices used in physical implementation and verification including sign-off (DRC/LEC/DFM/LVS/APC).
- Experience with RTL coding, Verilog, SystemVerilog, or VHDL.
- Strong scripting skills, such as python, perl or TCL.
- Skilled in the use test equipment for design validation, including spectrum analyzers, mixed-signal oscilloscopes, and logic analyzers.
- Excellent verbal and written communication skills.
- Experience in all aspects of physical design: floor planning, place and route, clock tree synthesis, and timing closure, low power and advanced node DFM methodologies, power analysis and signoff.
- Working knowledge of verification methodologies and UVM for simulation and debugging.
- Knowledgeable in the effects of radiation on circuit performance
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